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2300 mhz to 2900 mhz balanced mixer, lo buffer and rf balun adl5363 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features rf frequency range of 2300 mhz to 2900 mhz if frequency range of dc to 450 mhz power conversion loss: 7.7 db ssb noise figure of 7.6 db input ip3 of 31 dbm typical lo drive of 0 dbm single-ended, 50 rf and lo input ports high isolation spdt lo input switch single-supply operation: 3.3 v to 5 v exposed pad, 5 mm 5 mm 20-lead lfcsp 1500 v hbm/1250 v ficdm esd performance applications cellular base station receivers transmit observation receivers radio link downconverters general description the adl5363 uses a highly linear, doubly balanced passive mixer core along with integrated rf and local oscillator (lo) balancing circuitry to allow for single-ended operation. the adl5363 incorporates an rf balun to provide optimal performance over a 2300 mhz to 2900 mhz input frequency range. the balanced passive mixer arrangement provides good lo-to-rf leakage, typically better than ?30 dbm, and excellent intermodulation performance. the balanced mixer core also provides extremely high input linearity, allowing the device to be used in demanding cellular applications where in-band blocking signals might otherwise result in the degradation of dynamic performance. functional block diagram 2 3 1 20 19 18 17 16 6 7 8 9 10 4 5 14 13 15 12 bias generator vpmx rfin rfct comm comm loi2 vpsw vgs1 vgs0 loi1 v cmi ifop ifon pwdn comm vlo3 lgm3 vlo2 losw nc adl5363 nc = no connect 11 0 9914-001 figure 1. the adl5363 provides two switched lo paths that can be used in tdd applications where it is desirable to rapidly switch between two local oscillators. lo current can be externally set using a resistor to minimize dc current commensurate with the desired level of performance. for low voltage applications, the adl5363 is capable of operation at voltages down to 3.3 v with substantially reduced current. for low voltage operation, an additional logic pin is provided to power down (<200 a) the circuit when desired. the adl5363 is fabricated using a bicmos high performance ic process. the device is available in a 5 mm 5 mm, 20-lead lfcsp and operates over a ?40c to +85c temperature range. an evaluation board is also available. table 1. passive mixers rf frequency (mhz) single mixer single mixer and if amp dual mixer and if amp 500 to 1700 adl5367 adl5357 adl5358 1200 to 2500 adl5365 ADL5355 adl5356 2300 to 2900 adl5363 adl5353 adl5354
adl5363 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? 5 v performance........................................................................... 4 ? 3.3 v performance........................................................................ 4 ? absolute maximum ratings............................................................ 5 ? esd caution.................................................................................. 5 ? pin configuration and function descriptions............................. 6 ? typical performance characteristics ............................................. 7 ? 5 v performance........................................................................... 7 ? 3.3 v performance...................................................................... 14 ? upconversion.............................................................................. 15 ? spurious performance ............................................................... 16 ? circuit description......................................................................... 17 ? rf subsystem.............................................................................. 17 ? lo subsystem ............................................................................. 18 ? applications information .............................................................. 19 ? basic connections...................................................................... 19 ? if port .......................................................................................... 19 ? bias resistor selection ............................................................... 19 ? mixer vgs control dac .......................................................... 19 ? evaluation board ............................................................................ 20 ? outline dimensions ....................................................................... 23 ? ordering guide .......................................................................... 23 ? revision history 7/11 revision 0: initial version
adl5363 rev. 0 | page 3 of 24 specifications v s = 5 v, i s = 100 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, z o = 50 , unless otherwise noted. table 2. parameter test conditions/comments min typ max unit rf input interface return loss tunable to >20 db over a limited bandwidth 16 db input impedance 50 rf frequency range 2300 2900 mhz output interface output impedance differential impedance, f = 200 mhz 33||-0.3 ||pf if frequency range dc 450 mhz dc bias voltage 1 externally generated 3.3 5.0 5.5 v lo interface lo power ?6 0 +10 dbm return loss 15 db input impedance 50 lo frequency range 2330 3350 mhz power-down (pwdn) interface 2 pwdn threshold 1.0 v logic 0 level 0.4 v logic 1 level 1.4 v pwdn response time device enabled, if output to 90% of its final level 160 ns device disabled, supply current <5 ma 220 ns pwdn input bias current device enabled 0.0 a device disabled 70 a 1 apply the supply voltage from the external circuit through the choke inductors. 2 the pwdn function is intended for use with v s 3.6 v only.
adl5363 rev. 0 | page 4 of 24 5 v performance v s = 5 v, i s = 100 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. table 3. parameter test conditions/comments min typ max unit dynamic performance power conversion loss including 1:1 if port transformer and pcb loss 7.7 db ssb noise figure 7.6 db input third-order intercept (iip3) f rf1 = 2534.5 mhz, f rf2 = 2535.5 mhz, f lo = 2738 mhz, each rf tone at 0 dbm 31 dbm input second-order intercept (iip2) f rf1 = 2535 mhz, f rf2 = 2585 mhz, f lo = 2738 mhz, each rf tone at 0 dbm 62 dbm input 1 db compression point (ip1db) 1 exceeding 20 dbm rf power results in damage to the device 25 dbm lo-to-if leakage unfiltered if output ?22 dbm lo-to-rf leakage ?32 dbm rf-to-if isolation ?44 dbc if/2 spurious ?10 dbm input power ?61 dbc if/3 spurious ?10 dbm input power ?70 dbc power supply positive supply voltage 4.5 5 5.5 v quiescent current v s = 5 v 100 ma 1 exceeding 20 dbm rf power re sults in damage to the device. 3.3 v performance v s = 3.3 v, i s = 60 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, r9 = 226 , vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. table 4. parameter test conditions/comments min typ max unit dynamic performance power conversion loss including 1:1 if port transformer and pcb loss 7.4 db ssb noise figure 6.8 db input third-order intercept (iip3) f rf1 = 2534.5 mhz, f rf2 = 2535.5 mhz, f lo = 2738 mhz, each rf tone at 0 dbm 26 dbm input second-order intercept (iip2) f rf1 = 2535 mhz, f rf2 = 2585 mhz, f lo = 2738 mhz, each rf tone at 0 dbm 56 dbm power supply positive supply voltage 3.3 v quiescent current v s = 5 v 60 ma
adl5363 rev. 0 | page 5 of 24 absolute maximum ratings table 5. parameter rating supply voltage, v s 5.5 v rf input level 20 dbm lo input level 13 dbm ifop, ifon bias voltage 6.0 v vgs0, vgs1, losw, pwdn 5.5 v internal power dissipation 0.5 w thermal resistance, ja 25c/w temperature maximum junction temperature 150c operating temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature (soldering, 60 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adl5363 rev. 0 | page 6 of 24 pin configuration and fu nction descriptions pin 1 indicator notes 1. 2 nc = no connect. do not connect to this pin. . exposed pad. must be soldered to ground. 1 vpmx 2 rfin 3 rfct 4 comm 5 comm 13 vgs1 14 vpsw 15 loi2 12 vgs0 11 loi1 6 vlo3 7 lgm3 8 vlo2 10 nc 9 losw 18 ifon 19 ifop 20 vcmi 17 pw dn 16 comm top view (not to scale) adl5363 09914-002 figure 2. pin configuration table 6. pin function descriptions pin no. mnemonic description 1 vpmx positive supply voltage. 2 rfin rf input. must be ac-coupled. 3 rfct rf balun center tap (ac ground). 4, 5,16 comm device common (dc ground). 6, 8 vlo3, vlo2 positive supply voltages for lo amplifier. 7 lgm3 lo amplifier bias control. 9 losw lo switch. loi1 selected for 0 v, and loi2 selected for 3 v. 10 nc no connect. 11, 15 loi1, loi2 lo inputs. must be ac-coupled. 12, 13 vgs0, vgs1 mixer gate bias controls. 3 v logic. ground these pins for nominal setting. 14 vpsw positive supply voltage for lo switch. 17 pwdn power down. connect this pin to ground for normal operation and connect this pin to 3.0 v for disable mode. 18, 19 ifon, ifop differential if outputs. 20 vcmi no connect. this pin can be grounded. epad (ep) exposed pad. must be soldered to ground.
adl5363 rev. 0 | page 7 of 24 typical performance characteristics 5 v performance v s = 5 v, i s = 100 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. 105 104 103 102 101 100 99 98 97 96 95 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.902.852.802.752.70 supply current (ma) rf frequency (ghz) 09914-003 t a = ?40c t a = +25c t a = +85c figure 3. supply current vs. rf frequency 11 10 9 8 6 7 5 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.902.852.802.752.70 conversion loss (db) rf frequency (ghz) 09914-004 t a = +85c t a = +25c t a = ?40c figure 4. power conversion loss vs. rf frequency 40 38 36 34 30 28 26 24 22 32 20 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.902.852.802.752.70 input ip3 (dbm) rf frequency (ghz) 09914-005 t a = +85c t a = ?40c t a = +25c figure 5. input ip3 vs. rf frequency 90 85 80 75 65 60 55 50 45 70 40 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.902.852.802.752.70 input ip2 (dbm) rf frequency (ghz) 09914-006 t a = +85c t a = ?40c t a = +25c figure 6. input ip2 vs. rf frequency 10.0 9.5 8.5 8.0 7.5 7.0 6.5 9.0 5.0 6.0 5.5 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.902.852.802.752.70 ssb noise figure (db) rf frequency (ghz) 09914-007 t a = +85c t a = ?40c t a = +25c figure 7. ssb noise fi gure vs. rf frequency
adl5363 rev. 0 | page 8 of 24 v s = 5 v, i s = 100 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. 140 130 110 100 90 80 70 120 60 ?40 ?30 ?20 ?10 0 10 20 30 80 70 60 50 40 supply current (ma) temperature (c) 09914-008 5.25v 5.00v 4.75v figure 8. supply current vs. temperature 9.1 8.8 8.2 7.9 7.6 7.3 6.7 7.0 8.5 6.4 ?40 ?30 ?20 ?10 0 10 20 30 807060 5040 conversion loss (db) temperature (c) 09914-009 4.75v 5.00v 5.25v figure 9. power conversion loss vs. temperature 39 35 33 31 29 27 37 25 ?40 ?30 ?20 ?10 0 10 20 30 80706050 40 input ip3 (dbm) temperature (c) 09914-010 4.75v 5.00v 5.25v figure 10. input ip3 vs. temperature 74 71 65 62 59 56 53 68 50 ?40 ?30 ?20 ?10 0 10 20 30 8070605040 input ip2 (dbm) temperature (c) 09914-011 5.25v 4.75v 5.00v figure 11. input ip2 vs. temperature 10.0 9.5 8.5 8.0 7.5 7.0 6.5 9.0 5.0 6.0 5.5 ?40 ?30 ?20 ?10 0 10 20 30 8070605040 ssb noise figure (db) temperature (c) 09914-012 4.75v 5.00v 5.25v figure 12. ssb noise figure vs. temperature
adl5363 rev. 0 | page 9 of 24 v s = 5 v, i s = 100 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. 120 115 105 100 85 90 95 110 80 30 80 130 180 230 280 430 380 330 supply current (ma) if frequency (mhz) 09914-013 t a = +85c t a = ?40c t a = +25c figure 13. supply current vs. if frequency 8.4 8.2 8.0 7.8 7.2 7.4 7.6 7.0 30 80 130 180 230 280 430 380 330 conversion loss (db) if frequency (mhz) 09914-014 t a = +85c t a = ?40c t a = +25c figure 14. power conversion loss vs. if frequency 41 38 35 32 23 26 29 20 30 80 130 180 230 280 430 380 330 input ip3 (dbm) if frequency (mhz) 09914-015 t a = +85c t a = ?40c t a = +25c figure 15. input ip3 vs. if frequency 100 90 80 70 50 60 40 30 80 130 180 230 280 430 380 330 input ip2 (dbm) if frequency (mhz) 09914-016 t a = +85c t a = +25c t a = ?40c figure 16. input ip2 vs. if frequency 10.0 9.5 9.0 7.5 7.0 6.5 8.0 8.5 6.0 30 80 130 180 230 280 430 380 330 ssb noise figure (db) if frequency (mhz) 09914-017 figure 17. ssb noise figure vs. if frequency
adl5363 rev. 0 | page 10 of 24 v s = 5 v, i s = 100 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. 12 10 11 8 9 7 6 5 4 ?6 ?4 ?2 0 2 4 6 8 10 conversion loss (db) lo power (dbm) 09914-018 t a = ?40c t a = +25c t a = +85c figure 18. power conversion loss vs. lo power 36 34 32 30 28 26 24 22 20 ?6?4?20246810 input ip3 (dbm) lo power (dbm) 09914-019 t a = ?40c t a = +25c t a = +85c figure 19. input ip3 vs. lo power 80 70 60 50 40 30 20 10 0 ?6?4?20246810 input ip2 (dbm) lo power (dbm) 09914-020 t a = ?40c t a = +25c t a = +85c figure 20. input ip2 vs. lo power ? 30 ?35 ?40 ?45 ?50 ?55 ?60 ?65 ?70 ?75 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.902.852.802.752.70 if/2 spurious (dbc) rf frequency (ghz) 09914-021 t a = ?40c t a = +85c t a = +25c figure 21. if/2 spurio us vs. rf frequency ? 20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.902.852.802.752.70 if/3 spurious (dbc) rf frequency (ghz) 09914-022 t a = ?40c t a = +85c t a = +25c figure 22. if/3 spurio us vs. rf frequency
adl5363 rev. 0 | page 11 of 24 v s = 5 v, i s = 100 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. percentage (%) i supply (ma) 120 110 100 80 90 100 80 60 40 20 0 09914-023 mean: 101.06 sd: 0.0008% figure 23. supply current distribution percentage (%) conversion loss distribution (db) 7.2 7.6 7.4 7.8 8.2 8.0 100 80 60 40 20 0 09914-024 mean: 7.7 sd: 0.104% figure 24.conversion loss distribution percentage (%) input ip3 (dbm) 39 30 33 36 27 21 24 100 80 60 40 20 0 09914-025 mean: 31.13 sd: 0.286% figure 25. input ip3 distribution 50 0 50 0 30 430 resistance ( ? ) capacitance (pf) if frequency (mhz) 09914-026 ?4 ?3 ?2 ?1 0 1 2 3 4 5 10 15 20 25 30 35 40 45 80 130 180 230 280 330 380 resistance ( ? ) capacitance (pf) figure 26. if output impedanc e (r parallel, c equivalent) 0 ?2 ?4 ?6 ?10 ?12 ?14 ?16 ?18 ?8 ?20 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.902.852.802.752.70 rf return loss (db) rf frequency (ghz) 09914-027 figure 27. rf port return loss, fixed if 0 ?45 2.50 3.10 lo return loss (db) lo frequency (ghz) 09914-028 ?42 ?39 ?36 ?33 ?30 ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 selected unselected figure 28. lo return loss, selected and unselected
adl5363 rev. 0 | page 12 of 24 v s = 5 v, i s = 100 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. 60 57 54 51 48 45 42 39 36 33 30 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.902.85 2.802.75 2.70 lo switch isolation (db) rf frequency (ghz) 09914-029 t a = +85c t a = ?40c t a = +25c figure 29. lo switch isolation vs. rf frequency ? 30 ?35 ?40 ?45 ?55 ?50 ?60 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.902.852.802.752.70 rf-to-if isolation (dbc) rf frequency (ghz) 09914-030 t a = ?40c t a = +85c t a = +25c figure 30. rf-to-if isolation vs. rf frequency ? 5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 2.50 2.55 2.60 2.65 2.70 2.75 2.80 3.10 3.00 3.05 2.952.902.85 lo-to-if leakage (dbm) lo frequency (ghz) 09914-031 t a = +85c t a = ?40c t a = +25c figure 31. lo-to-if leakage vs. lo frequency 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 ?45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 3.10 3.00 3.05 2.952.902.85 lo-to-if leakage (dbm) lo frequency (ghz) 09914-032 t a = +85c t a = ?40c t a = +25c figure 32. lo-to-rf leakage vs. lo frequency 0 ?5 ?10 ?15 ?20 ?25 ?30 ?60 ?55 ?50 ?45 ?40 ?35 2xlo leakage (dbm) 09914-033 2xlo to rf 2xlo to if 2.50 3.10 lo frequency (ghz) 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 figure 33. 2lo leakag e vs. lo frequency ? 52 ?55 ?58 ?61 ?76 ?67 ?70 ?73 ?64 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3xlo leakage (dbm) lo frequency (ghz) 09914-034 3xlo to rf 3xlo to if figure 34. 3lo leakag e vs. lo frequency
adl5363 rev. 0 | page 13 of 24 v s = 5 v, i s = 100 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. 12 11 10 9 8 7 6 5 4 3 2 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.902.852.802.752.70 conversion gain (db) rf frequency (ghz) 09914-035 23 3 7 5 9 11 13 15 17 19 21 ssb noise figure (db) vgs = 0, 0 vgs = 0, 1 vgs = 1, 0 vgs = 1, 1 gain noise figure figure 35. power conversion loss and ssb noise figure vs. rf frequency 40 38 36 34 30 28 26 24 22 32 20 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.902.852.802.752.70 input ip3 (db m ) rf frequency (ghz) 09914-036 vgs = 0, 0 vgs = 0, 1 vgs = 1, 0 vgs = 1, 1 figure 36. input ip3 vs. rf frequency 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 32 31 30 29 28 27 26 25 24 600 700 900800 1000 1100 1200 1300 1400 1500 1600 1700 1800 conversion loss and ssb noise figu r e(db) input ip3 (dbm) bias resistor value ( ? ) 09914-037 conversion loss (db) noise figure (db) input ip3 (dbm) figure 37. power conversion loss, ssb noise figure, and input ip3 vs. if bias resistor value 140 130 120 110 100 90 80 70 60 600 1800 supply current (ma) bias resistor value ( ? ) 09914-038 700 900800 1000 1100 1200 1300 1400 1500 1600 1700 figure 38. supply current vs. bias resistor value
adl5363 rev. 0 | page 14 of 24 3.3 v performance v s = 3.3 v, i s = 60 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. 67 65 63 61 57 59 56 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.902.852.802.752.70 supply current (ma) rf frequency (ghz) 09914-039 t a = +25c t a = ?40c t a = +85c figure 39. supply current vs. rf frequency at 3.3 v 9.0 8.5 8.0 7.5 7.0 6.5 5.0 5.5 6.0 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.902.852.802.752.70 conversion loss (db) rf frequency (ghz) 09914-040 t a = +85c t a = ?40c t a = +25c figure 40. power conversion loss vs. rf frequency at 3.3 v 34 31 28 25 22 19 10 13 16 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.902.852.802.752.70 input ip3 (dbm) rf frequency (ghz) 09914-041 t a = +85c t a = ?40c t a = +25c figure 41. input ip3 vs. rf frequency at 3.3 v 100 90 80 70 60 50 20 30 40 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.902.852.802.752.70 input ip2 (dbm) rf frequency (ghz) 09914-042 t a = ?40c t a = +85c t a = +25c figure 42. input ip2 vs. rf frequency at 3.3 v 9.0 8.5 8.0 7.0 7.5 4.0 4.5 5.0 5.5 6.0 6.5 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.902.852.802.752.70 ssb noise figure (db) frequency (ghz) 09914-043 t a = ?40c t a = +85c t a = +25c figure 43. ssb noise figure vs. rf frequency at 3.3 v
adl5363 rev. 0 | page 15 of 24 upconversion v s = 5 v, i s = 100 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. 13 12 11 10 9 8 7 6 5 4 3 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.90 2.85 2.802.752.70 conversion loss (db) rf frequency (ghz) 09914-044 t a = +85c t a = ?40c t a = +25c figure 44. power conversion loss vs. rf frequency, v s = 5 v, upconversion 30 29 28 27 26 25 24 23 22 21 20 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.90 2.852.80 2.752.70 input ip3 (dbm) rf frequency (ghz) 09914-045 t a = +25c t a = +85c t a = ?40c figure 45. input ip3 vs. rf frequency, v s = 5 v, upconversion 9.0 8.5 8.0 7.5 7.0 6.5 5.5 6.0 5.0 4.5 4.0 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.902.85 2.802.75 2.70 conversion loss (db) rf frequency (ghz) 09914-046 t a = +25c t a = ?40c t a = +85c figure 46. power conversion loss vs. rf frequency at 3.3 v, upconversion 35 33 31 29 27 25 21 23 19 17 15 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.90 2.85 2.802.752.70 input ip3 (dbm) rf frequency (ghz) 09914-047 t a = ?40c t a = +85c t a = +25c figure 47. input ip3 vs. rf frequency at 3.3 v, upconversion
adl5363 rev. 0 | page 16 of 24 spurious performance (n f rf ) ? (m f lo ) spur measurements were made using th e standard evaluation board. mixer spurious products are measured in dbc from the if output power level. data was measured only for frequencies less than 6 gh z. typical noise floor of the measurement system = ?100 dbm. 5 v performance v s = 5 v, i s = 100 ma, t a = 25c, f rf = 2535 mhz, f lo = 2738 mhz, lo power = 0 dbm, rf power = 0 dbm, vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. m 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 ?10.9 ?28.3 ?44.5 1 ?42.2 0.0 ?49.3 ?31.2 ?49.8 2 ?75.8 ?76.5 ?64.6 ?78.4 ?78.5 ?94.7 3 adl5363 rev. 0 | page 17 of 24 circuit description rf subsystem the adl5363 consists of two primary components: the radio frequency (rf) subsystem and the local oscillator (lo) subsystem. the combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die, using mature packaging and interconnection technologies to provide a high performance, low cost design with excellent electrical, mechanical, and thermal properties. in addition, the need for external components is minimized, optimizing cost and size. the single-ended, 50 rf input is internally transformed to a balanced signal using a low loss (<1 db) unbalanced-to-balanced (balun) transformer. this transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the rf port. although the port can be dc connected, it is recommended that a blocking capacitor be used to avoid running excessive dc current through the part. the rf balun can easily support an rf input frequency range of 2300 mhz to 2900 mhz. the rf subsystem consists of an integrated, low loss rf balun, passive mosfet mixer, sum termination network. the resulting balanced rf signal is applied to a passive mixer that commutates the rf input with the output of the lo subsystem. the passive mixer is essentially a balanced, low loss switch that adds minimum noise to the frequency translation. the only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms. the lo subsystem consists of an spdt-terminated fet switch and a three-stage limiting lo amplifier. the purpose of the lo subsystem is to provide a large, fixed amplitude, balanced signal to drive the mixer independent of the level of the lo input. a block diagram of the device is shown in figure 48 . as the mixer is inherently broadband and bidirectional, it is necessary to properly terminate all the idler (m n product) frequencies generated by the mixing process. terminating the mixer avoids the generation of unwanted intermodulation products and reduces the level of unwanted signals at the if output. this termination is accomplished by the addition of a sum network between the if output and the mixer. 2 3 1 20 19 18 17 16 6 7 8 9 10 4 5 14 13 15 12 bias generator vpmx rfin rfct comm comm loi2 vpsw vgs1 vgs0 loi1 v cmi ifop ifon pwdn comm vlo3 lgm3 vlo2 losw nc adl5363 nc = no connect 11 09914-051 the ip3 performance can be optimized by adjusting the supply current with an external resistor. figure 37 and 38 illustrate how the bias resistor affects the performance with a 5 v supply. additionally, dc current can be saved by increasing either or both resistors. it is permissible to reduce the dc supply voltage to as low as 3.3 v, further reducing the dissipated power of the part. (note that no performance enhancement is obtained by reducing the value of these resistors and excessive dc power dissipation may result.) figure 48. simpli fied schematic
adl5363 rev. 0 | page 18 of 24 lo subsystem the adl5363 has two lo inputs permitting multiple synthesizers to be rapidly switched with extremely short switching times (<40 ns) for frequency agile applications. the two inputs are applied to a high isolation spdt switch that provides a constant input impedance, regardless of whether the port is selected, to avoid pulling the lo sources. this multiple section switch also ensures high isolation to the off input, minimizing any leakage from the unwanted lo input that may result in undesired if responses. the single-ended lo input is converted to a fixed amplitude differential signal using a multistage, limiting lo amplifier. this results in consistent performance over a range of lo input power. optimum performance is achieved from ?6 dbm to +10 dbm, but the circuit continues to function at considerably lower levels of lo input power. the performance of this amplifier is critical in achieving a high intercept passive mixer without degrading the noise floor of the system. this is a critical requirement in an interferer rich environment, such as cellular infrastructure, where blocking interferers can limit mixer performance. the bandwidth of the intermodulation performance is somewhat influenced by the current in the lo amplifier chain. for dc current sensitive applications, it is permissible to reduce the current in the lo amplifier by raising the value of the external bias control resistor. for dc current critical applications, the lo chain can operate with a supply voltage as low as 3.3 v, resulting in substantial dc power savings. in addition, when operating with supply voltages below 3.6 v, the adl5363 has a power-down mode that permits the dc current to drop to <200 a. all of the logic inputs are designed to work with any logic family that provides a logic 0 input level of less than 0.4 v and a logic 1 input level that exceeds 1.4 v. all logic inputs are high impedance up to logic 1 levels of 3.3 v. at levels exceeding 3.3 v, protection circuitry permits operation up to 5.5 v, although a small bias current is drawn. all pins, including the rf pins, are esd protected and have been tested up to a level of 1500 v hbm and 1250 v cdm.
adl5363 rev. 0 | page 19 of 24 applications information basic connections the adl5363 mixer is designed to downconvert radio frequen- cies (rf) primarily between 2300 mhz and 2900 mhz to lower intermediate frequencies (if) between 30 mhz and 450 mhz. figure 49 depicts the basic connections of the mixer. to prevent nonzero dc voltages from damaging the rf balun or lo input circuit, ac-couple the rf and lo input ports. the rfin matching network consists of a series 1.5 pf capacitor and a shunt 12 nh inductor to provide the optimized rf input return loss for the desired frequency band. if port the real part of the output impedance is approximately 50 , as seen in figure 26 , which matches many commonly used saw filters without the need for a transformer. this results in a voltage conversion loss that is approximately the same as the power conversion loss, as shown in table 3 . bias resistor selection an external resistor, r bias lo , is used to adjust the bias current of the integrated amplifiers at the lo terminals. it is necessary to have a sufficient amount of current to bias the internal lo amplifier to optimize dc current vs. optimum iip3 performance. figure 37 and figure 38 provide the reference for the bias resistor selection when lower power consumption is considered at the expense of conversion gain and ip3 performance. mixer vgs control dac the adl5363 features two logic control pins, vgs0 (pin 12) and vgs1 (pin 13), that allow programmability for internal gate-to- source voltages for optimizing mixer performance over desired frequency bands. the evaluation board defaults both vgs0 and vgs1 to ground. 2 3 1 19 18 17 16 6 7 8 9 10 14 15 12 11 bias generator lo2_in rf-in +5v +5v +5v +5v lo1_in 10k ? r1 0 ? c24 560pf 10k ? 10pf 10pf 10pf 1.5pf 10pf 10h 0.01f 4.7f r bias lo 22pf 10pf 22pf adl5363 20 13 5 4 09914-052 t1 if1_out c25 560pf 12nh figure 49. typical application circuit
adl5363 rev. 0 | page 20 of 24 evaluation board an evaluation board is available for the family of double balanced mixers. the standard evaluation board schematic is shown in figure 50 . the evaluation board is fabricated using rogers? ro3003 material. table 7 describes the various configuration options of the evaluation board. evaluation board layout is shown in figure 51 to figure 54 . 0 9914-053 c22 1nf c20 10pf c2 10f c21 10pf c1 1.5pf c10 22pf c12 22pf vgs1 lo2_in lo1_in rf-in r22 10k ? vpos pwr_up r23 15k ? vpos vpos vpos losel vgs0 c5 0.01f c4 10pf c6 10pf c8 10pf r9 1.1k ? r4 10k ? r21 10k ? r14 0 ? l3 0 ? vpmx rfin rfct comm comm vgs1 vpsw loi2 vgs0 loi1 ifon ifop vcmi pw dn comm vlo3 lgm3 v lo2 nc losw adl5363 r1 0 ? c24 560pf t1 if1_out c25 560pf z1 12nh figure 50. evaluation board schematic
adl5363 rev. 0 | page 21 of 24 table 7. evaluation board configuration components function description default conditions c2, c6, c8, c20, c21 power supply decoupling power supply decoupling. nominal supply decoupling consists of a 10 f capacitor to ground in parallel with a 10 pf capacitor to ground positioned as close to the device as possible. c2 = 10 f (size 0603), c6, c8, c20, c21 = 10 pf (size 0402) c1, c4, c5, z1 rf input interface rf input interface. the input channels are ac-coupled through c1. c4 and c5 provide bypassing for the center taps of the rf input baluns. c1 = 1.5 pf (size 0402), c4 = 10 pf (size 0402), c5 = 0.01 f (size 0402) z1= 12 nh (size 0402) t1, r1, c24, c25 if output interface if output interface. t1 is a 1:1 impedance transformer used to provide a single-ended if output interface. remove r1 for balanced output operation. c24 and c25 are used to block the dc bias at the if ports. t1 = tc1-1-13m+ (mini-circuits), r1 = 0 (size 0402), c24, c25 = 560 pf (size 0402) c10, c12, r4 lo interface lo interface. c10 and c12 provide ac coupling for the lo1_in and lo2_in local oscillator inputs. losel selects the appropriate lo input for both mixer cores. r4 provides a pull-down to ensure that lo1_in is enabled when the losel test point is logic low. lo2_in is enabled when losel is pulled to logic high. c10, c12 = 22 pf (size 0402), r4 = 10 k (size 0402) r21 pwdn interface pwdn interface. r21 pulls the pwdn logic low and enables the device. the pwr_up test point allows the pwdn interface to be exercised using the an external logic generator. grounding the pwdn pin for nominal operation is allowed. using the pwdn pin when supply voltages exceed 3.3 v is not allowed. r21 = 10 k (size 0402) c22, l3, r9, r14, r22, r23, vgs0, vgs1 bias control bias control. r22 and r23 form a voltage divider to provide 3 v for logic control, bypassed to ground through c22. vgs0 and vgs1 jumpers provide programmability at the vgs0 and vgs1 pins. it is recommended to pull these two pins to ground for nominal operation. r9 sets the bias point for the internal lo buffers. c22 = 1 nf (size 0402), l3 = 0 (size 0603), r9 = 1.1 k (size 0402), r14 = 0 (size 0402), r22 = 10 k (size 0402), r23 = 15 k (size 0402), vgs0 = vgs1 = 3-pin shunt
adl5363 rev. 0 | page 22 of 24 09914-152 figure 51. evaluation board top layer 09914-153 figure 52. evaluation board ground plane, internal layer 1 09914-154 figure 53. evaluation board power plane, internal layer 2 09914-155 figure 54. evaluation board bottom layer
adl5363 rev. 0 | page 23 of 24 outline dimensions compliant to jedec standards mo-220-vhhc 042209-b 1 0.65 bsc p i n 1 i n d i c a t o r 2.60 bsc 0.75 0.60 0.50 top view 12 max seating plane pin 1 indi c ator coplanarity 0.05 0.90 0.85 0.80 0.35 0.28 0.23 0.05 max 0.01 nom 0.20 ref 0.70 0.65 0.60 3.20 3.10 sq 3.00 20 6 16 10 11 15 5 exposed pad (bottom view) 0.60 max 0.60 max 5.00 bsc sq 4.75 bsc sq for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 55. 20-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-20-5) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ordering quantity adl5363acpz-r7 ?40c to +85c 20-lead lead frame chip scale package [lfcsp_vq] 7 tape and reel cp-20-5 1,500 adl5363-evalz evaluation board 1 1 z = rohs compliant part.
adl5363 rev. 0 | page 24 of 24 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09914-0-7/11(0)

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